60 GHz PLL

The 60 GHz PLL IP performs low noise RF frequency synthesis for wireless communications applications. It can be used to implement local oscillators (LO) in the up-conversion and down-conversion sections of wireless receivers and transmitters

Register-Controlled Delay-Locked Loop (RCDLL)

The Register-Controlled Delay-Locked Loop (RCDLL) is an all-digital semiconductor intellectual property (SIP) module that can be used to generate 0o, 90o, 180o, and 270o clock phases The RCDLL design is specialized for use with Double Data Rate Physical Interfaces (DDR PHYs) enabling seamless operation between 200-800MHz

Low Voltage Differential Signaling (LVDS) Driver

Low Voltage Differential Signaling (LVDS) is a 2.5V supply high speed IO interface mainly used for digital ICs

DDR2/3 SSTL Driver

Series Stub Terminated Logic (SSTL) is a 1.8V supply IO interface mainly used for digital ICs. Analogies SSTL IP meets all the JEDEC JESD8-15A specification requirements and includes enhanced functions such as: driver pre-emphasis, slew rate control and power saving mode

Differential Distributed VCO (DDVCO)

Analogies patent enforced Differential Distributed Voltage-Controlled Oscillator (DDVO) is implemented in a 0.35 um 4P4M SiGe BiCMOS technology with an ft of 60 GHz

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