Analogies have developed a wide variety of silicon IPs optimized for low power and high performance including:

  • Analog IPs low power, high performance ADC/DAC, VCOs, Voltage reference (Bandgaps), charge pumps frequency dividers and High Speed MUX/DEMUX
  • Foundation IPs High speed 60G PLL for wireless communication application, an all digital RCDLL and a DDR2/3 SSTL driver
  • Interface IPs emphasizing in high speed front end PHYs (SerDes, DDR2/3, USB 3.0 PHY) for wireline & wireless communication applications
  • ECC/FEC Digital/Mixed-signal implementations of signal processing algorithms on error correcting FEC codes, with emphasis in Turbo/LDPC like correcting schemes for wireless backhaul and wireline applications

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